Today's computing architectures are designed to provide the sophisticated computer user with increased Reliability, Availability, and Scalability (RAS). To that end, the rise of operating environments, such as the Microsoft Windows NT/2000 operating environments, have presented a relatively low cost solution to the traditional high-end computing environment. The introduction of the Enterprise Edition has extended the scalability and resilience of the NT Server to provide a powerful and attractive solution to today's largest and most mission critical applications.
The Cellular MultiProcessing (CMP) architecture is a software/hardware environment that is developing as the enabling architecture that allows servers such as Windows NT/2000-based servers to perform in such mission critical solutions. The CMP architecture incorporates high performance processors using special hardware and middleware components that build on standard interface components to expand the capabilities of the Microsoft Windows server operating systems. The CMP architecture utilizes a Symmetric MultiProcessor (SMP) design, which employs multiple processors supported by high throughput memory, Input/Output (I/O) systems and supporting hardware elements to bring about the manageability and resilience required for enterprise class servers.
Key to the CMP architecture is its ability to provide multiple, independent partitions, each with their own physical resources and operating system. Partitioning requires the flexibility required to support various application environments with increased control and greater resilience. Multiple server applications can be integrated into a single platform with improved performance, superior integration and lower costs to manage.
The objectives of the CMP architecture are multifold. These objectives may include, for example, providing scaling of applications beyond what is normally possible when running Microsoft Windows server operating systems on an SMP system; improving the performance, reliability and manageability of a multiple application node by consolidating them on a single, multi-partition system; establishing new levels of RAS for open servers in support of mission critical applications; and providing new levels of interoperability between operating systems through advanced, shared memory techniques.
The concept of multiprocessors sharing the workload in a computer relies heavily on shared memory. True SMP requires each processor to have access to the same physical memory, generally through the same system bus. When all processors share a single image of the memory space, that memory is said to be coherent, where data retrieved by each processor from the same memory address is identical. Coherence is threatened, however, by the widespread use of onboard, high speed cache memory. When a processor reads data from a system memory location, it stores that data in high speed cache. A successive read from the same system memory address results instead, in a read from the cache, in order to provide an improvement in access speed. Likewise, writes to the same system memory address results instead to writes to the cache, which ultimately leads to data incoherence between the cache and system memory.
Off-board cache, e.g., fourth level (L4) cache, may also be used in typical SMP designs, whereby multiple processors not only have access to shared system memory, but also to the L4 cache implemented, for example, using Static Random Access Memory (SRAM). Prior art methods of verifying that the SRAM used for L4 cache is operating correctly primarily consists of two methods. A first method involves general purpose SRAM test bed facilities that are implemented external to the system in which the SRAM will be used. Another method includes internal software test facilities executed by one of the processors in the SMP system.
A drawback of the first prior art method of L4 cache verification is that it does not test the SRAM under the same conditions that the SRAM will be used. For example, memory test beds may be implemented whereby different interconnect methods, thermal conditions, timing relationships, and usage patterns are such that adequate performance may be verified while the SRAM is installed in the test bed, but fails while the SRAM is operating under actual usage conditions.
Prior art software facilities, while allowing SRAM tests to be conducted under normal operating conditions, fail to provide adequate flexibility and controllability to the test procedure. Testing SRAM via software requires navigation through multiple layers of software and hardware to perform the tests, which severely limits test control and flexibility. Further, software controlled operation of an SRAM test facility generally requires more time to execute than the hardware controlled counterpart, while also limiting the amount of control that may be exercised over the actual test procedure used for memory verification.
Therefore, a need to facilitate testing of off-board cache memory under normal operating conditions is desirable, while also providing the control, flexibility, and speed of an on-board, hardware based cache memory exerciser. The present invention provides a solution to these and other shortcomings of the prior art, and offers numerous advantages over prior art approaches.